Data Cache-Energy and Throughput Models: Design Exploration for Embedded Processors

Most modern 16-bit and 32-bit embedded processors contain cache memories to further increase instruction throughput of the device. Embedded processors that contain cache memories open an opportunity for the low-power research community to model the impact of cache energy consumption and throughput gains. For optimal cache memory configuration mathematical models have been proposed in the past. Most of these models are complex enough to be adapted for modern applications like run-time cache reconfiguration. This paper improves and validates previously proposed energy and throughput models for a data cache, which could be used for overhead analysis for various cache types with relatively small amount of inputs. These models analyze the energy and throughput of a data cache on an application basis, thus providing the hardware and software designer with the feedback vital to tune the cache or application for a given energy budget. The models are suitable for use at design time in the cache optimization process for embedded processors considering time and energy overhead or could be employed at runtime for reconfigurable architectures

Renewal theory sleep time optimisation for scheduling events in Wireless Sensor Networks

This paper addresses the problem of optimised decision making in scheduling non deterministic events for WSN nodes. Scheduling events for highly constrained WSN nodes with finite resources can significantly increase the lifetime of the network. Optimising the scheduling of events ensures that under any given constraint the network lifetime is maximised. The presented technique uses Renewal theory to formulate a stochastic decision making process. By observing network events, optimised decisions are made regarding node sleep times. This technique links the time a node spends in the sleep state to the rate of traffic throughput in the network making the process able to adapt to changes. The proposed technique also has the added advantage of using data available locally to a node thus minimising control overheads. It can be employed in both static and ad hoc networks, as well as for autonomous decision making in nodes that have to self configure. Finally, this policy driven technique exploits the heterogeneous nature of a typical WSN architecture by using less constrained nodes for formulating policies which can then be implemented in more constrained nodes. Theoretical and empirical results are presented

ICMetrics based industrial internet of things (IIoT) security in the post quantum world

We are moving into an era of autonomous Industrial Internet of Things world; its security must be considered a crucial element. To maintain the current growth rate in Industrial Internet of Things, future threats related to quantum computing era need utmost attention. This research, in its preliminary stages is a major step in this direction and aims to design an ICMetrics based Industrial Internet of Things security framework for the post quantum era

Improving Resilience Against Node Capture Attacks in Wireless Sensor Networks Using ICmetrics

Wireless Sensor Networks (WSNs) have the potential of being employed in a variety of applications ranging from battlefield surveillance to everyday applications such as smart homes and patient monitoring. Security is a major challenge that all applications based on WSNs are facing nowadays. Firstly, due to the wireless nature of WSNs, and secondly due to their ability to operate in unattended environments makes them even more vulnerable to various sorts of attacks. Among these attacks is node capture attack in WSNs, whose threat severity can range from a single node being compromised in the network to the whole network being compromised as a result of that single node compromise. In this paper, we propose the use of ICMetric technology to provide resilience against node compromise in WSN. ICmetrics generates the security attributes of the sensor node based on measurable hardware and software characteristics of the integrated circuit. These properties of ICmetrics can help safeguard WSNs from various node capture attacks

An ICMetrics Based Lightweight Security Architecture Using Lattice Signcryption

The advent of embedded systems has completely transformed the information landscape. With the explosive growth in the use of interactive real-time technologies, this internet landscape aims to support an even broader range of application domains. The large amount of data that is exchanged by these applications has made them an attractive target for attacks. Thus it is important to employ security mechanisms to protect these systems from attackers. A major challenge facing researchers is the resource constrained nature of these systems, which renders most of the traditional security mechanisms almost useless. In this paper we propose a lightweight ICmetrics based security architecture using lattices. The features of the proposed architecture fulfill both the requirements of security as well as energy efficiency. The proposed architecture provides authentication, confidentiality, non-repudiation and integrity of data. Using the identity information derived from ICmetrics of the device, we further construct a sign cryption scheme based on lattices that makes use of certificate less PKC to achieve the security requirements of the design. This scheme is targeted on resource constrained environments, and can be used widely in applications that require sufficient levels of security with limited resources

Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review

The technological evolution has increased the number of transistors for a given die area significantly and increased the switching speed from few MHz to GHz range. Such inversely proportional decline in size and boost in performance consequently demands shrinking of supply voltage and effective power dissipation in chips with millions of transistors. This has triggered substantial amount of research in power reduction techniques into almost every aspect of the chip and particularly the processor cores contained in the chip. This paper presents an overview of techniques for achieving the power efficiency mainly at the processor core level but also visits related domains such as buses and memories. There are various processor parameters and features such as supply voltage, clock frequency, cache and pipelining which can be optimized to reduce the power consumption of the processor. This paper discusses various ways in which these parameters can be optimized. Also, emerging power efficient processor architectures are overviewed and research activities are discussed which should help reader identify how these factors in a processor contribute to power consumption. Some of these concepts have been already established whereas others are still active research areas. © 2009 ACADEMY PUBLISHER

Analytical Evaluation of Energy and Throughput for Multilevel Caches

With the increase of processor-memory performance gap, it has become important to gauge the performance of cache architectures so as to evaluate their impact on energy requirement and throughput of the system. Multilevel caches are found to be increasingly prevalent in the high-end processors. Additionally, the recent drive towards multicore systems has necessitated the use of multilevel cache hierarchies for shared memory architectures. This paper presents simplified and accurate mathematical models to estimate the energy consumption and the impact on throughput for multilevel caches for single core systems